About The Business:

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.’

Role Overview:

The SME – Senior Test Cell Development Engineer acts as the technical authority for test cell architecture, deployment, and optimization in wafer sort and final test environments. This role combines deep subject matter expertise with leadership responsibilities, ensuring robust test coverage, high throughput, and cost‑effective test solutions across NPI and high‑volume manufacturing.

Key Responsibilities

Test Cell Architecture & Development:

• Define and design test cell configurations (ATE, probers, handlers, sockets, automation interfaces).
• Lead qualification and release of new test cells for wafer sort and final test.
• Ensure scalability, repeatability, and maintainability of test cell designs.
• Design and develop test cell configuration, docking/undocking handlers and probers, including hardware change kits for NPI programs & production ramp-ups.
• Assist with test floor tool setup, ensure smooth transition from NPI to production by buying off new hardware and clarifying constraints  
• Handler and Prober change Kits development and setup and manage teams

• Architect and deploy automated test cells for wafer sort and final test.
• Familiar with all the testers (Advantest (93K), Teradyne Ultra Flex/J750, Eagle ETS, Nextest, Advantest), Handler/Probers Good Knowledge working on Handler (Hon Precision, Delta Matrix), probers (TEL, Accretes) and identifying the Handler & Prober for the NPI devices, sockets for the devices, burn-in equipment’s and process
• Ensure scalability, repeatability, and robustness of test cell designs.
• Integrate test cells with OSAT production lines, balancing throughput, cost, and reliability.
• Oversee qualification and release of new test platforms and equipment.
• Continuous Improvement - Suggest DOE/project actions to improve uptime & yield
• Collaboration & Coordination - Engage with NPI, planning, engineering, spare-stock teams
• Hands-on troubleshooting skills for handlers, probers, sockets, probe cards, and load boards.

Handler & Prober Change Kit Management:

• Assist in managing handler docking, qualification of multiple change kits, and maintaining documentation for hardware swaps during ramp-up and product transitions.

• Localize the Change Kits

NPI & Technology Transfer:

• Support new product introduction (NPI) by developing test cell solutions aligned with product requirements.
• Drive smooth transfer of test cells from engineering to high‑volume manufacturing.

Key Performance Indicators (KPIs):

• On‑time qualification and release of new test cells.
• Improvement in first‑pass yield and reduction in retest rates.
• Reduction in test cycle time and cost per device.
• Successful NPI ramp‑up with robust test cell deployment.
• Positive customer audit outcomes  

Subject Matter Expertise & Leadership:

• Act as SME for test cell development, mentoring junior engineers and technicians.
• Provide technical guidance during customer audits, reviews, and escalations.
• Collaborate with ATE vendors and OSAT partners to evaluate new technologies.

Essential Attributes:

Technical Skills:

• Expertise in ATE platforms (Teradyne, Advantest, Cohu, SPEA).
• Deep knowledge of wafer probers, handlers, sockets, and probe card technologies.
• Proficiency in test data analysis tools (Python, JMP, Minitab).

Process Skills:

• Lean/Six Sigma, SPC, FMEA, project management.

Soft Skills:

• Leadership, mentoring, customer communication, problem‑solving.\

Qualifications:

• B.E./B.Tech in Electronics, Electrical, Instrumentation, or related field; M.E./M.Tech preferred.

Desired Experience Level:

• 6–10 years in semiconductor test engineering, with at least 4 years in test cell development and deployment.